1. Field of the Invention
The present invention relates to an intermediate substrate and, more particularly, to an intermediate substrate for a semiconductor integrated circuit device.
2. Description of the Related Art
Semiconductor integrated circuit devices operating at high speeds, such as CPUs and other LSIs, have been much reduced in size in recent years, whereas the number of signal terminals, power source terminals and ground terminals has been increasing, and the terminal interval, i.e., the spacing between terminals, is becoming smaller or narrower. A terminal array on the integrated circuit side, which is typically comprised of packed multiple terminals, is generally connected to the mother board side of a flip-chip form, but because the terminal interval of the integrated circuit side terminal is significantly different from that of the mother board side terminal array, an intermediate substrate is required to accommodate this difference.
Such intermediate substrates include the so-called organic package substrate, which comprises a laminated wiring section comprising alternately laminated dielectric layer(s) made of a polymeric material and conductor layer(s), and a terminal array for flip-chip connection disposed on a first principal surface formed in the dielectric layer of the laminated wiring section. The laminated wiring section formed on a substrate core is principally comprised of a polymeric material such as an epoxy resin reinforced with glass fibers. If there is a substantial gap between the IC side terminal interval and the terminal interval at the main substrate (mother board) side at the point of connection, the wiring and via disposition pattern for providing the necessary conversion tends to be both fine (very dense) and complex. Further, an additional problem is presented by the increase in the number of terminals. However, the organic package substrate is advantageous because such a fine and complex wiring pattern can be easily formed with high precision, using a combination of photolithography technology and plating technology.
However, since the organic package substrate is comprised of a polymeric material, when the substrate is connected to the main substrate (for example, the mother board) which is principally made of a polymeric material, and taking into account the thermal history of the solder reflow operation or the like, the difference in the coefficient of linear expansion between the semiconductor integrated circuit device, which is principally made of silicon (having a coefficient of linear expansion of, for example, 2 to 3 ppm/° C.), and the main substrate (having a coefficient of linear expansion of, for example, 17 to 18 ppm/° C.) cannot be accommodated, and thus may lead to disconnection caused by solder peeling and/or other defects.
Japanese unexamined patent publication No. 2001-035966 discloses a ceramic package substrate principally comprised of ceramics. By using such a ceramic package substrate, the difference in coefficient of linear expansion between the semiconductor integrated circuit device and the main substrate connected by a flip-chip connection, can be substantially eliminated, and defects such as disconnection caused by thermal stress at the solder junction between the semiconductor integrated circuit device and the associated terminals can be effectively prevented.
However, because, in the ceramic package substrate, the wiring is provided by printing and baking a metal paste, it is hard to form fine wiring patterns with high integration, in contrast to organic package substrates which are formed using photolithography technology. Thus, the ceramic package substrate is limited in its ability to reduce the terminal interval at the semiconductor integrated circuit device side. Hence, a multilayer substrate connection structure may be provided by connecting a first intermediate substrate made of an organic package substrate at the main substrate side, connecting a second “relay” substrate made of ceramic to the first intermediate substrate, and connecting a semiconductor integrated circuit device to the second relay substrate. However, as the number of intermediate substrates is increased, the height dimension of the substrate connection structure is increased. This is a serious disadvantage because of the current demand for size reduction. In addition, the number of steps required in the connection process is increased, and production efficiency is sacrificed.